Yahara Mitsutoshi

論文

Proposal of a high-speed Hamming distance detector using electronic neuron circuit and chip evaluation

DIGITAL FREQUENCY-LOCKED LOOP WITH WIDE LOCK-IN RANGE AND LOW FREQUENCY ERROR BASED ON MULTI-PHASE CLOCK

APPROACHES TO REMOTE LEARNING DURING COVID-19 IN THE SCHOOL OF INDUSTRIAL AND WELFARE ENGINEERING, TOKAI UNIVERSITY

An Electronic Neuron Using Interconnect Capacitance and Applied to a Variable Logic Circuit

Digital Frequency-Locked Loop with Low Frequency Error Based on Multi-Phase Clock

A Study of Digitally Controlled Oscillator Based on Multi-Phase Clock

Digital Frequency-Locked Loop Based on Double-Edge Counter

A flash type a/d converter using neuron cmos inverters with threshold compensation circuits

A RESET TYPE 2-MODE DIGITAL FLL WITH ANTI-PSEUDO-LOCK FUNCTION AND PHASE CONTROL

A 1+n/k Frequency Divider Unrelated to Duty Ratio of Multi-Phase Clock

A DIGITALLY CONTROLLED OSCILLATOR USING 1+1/k FREQUENCY DIVIDER BASED ON MULTI-PHASE CLOCK

A study of 1 + N/K frequency divider based on multi-phase clock with extended division ratio

A Study of 1+n/k Frequency Divider Based on Multi-Phase Clock

Multiple-frequency digital phase-locked loop based on multiphase clock divider with constant pulse interval

Multiple Frequency Digital Phase-Locked Loop Based on Multi-Phase Clock Divider with Constant Pulse Interval

A 2-MODE DIGITAL FLL USING FREQUENCY COMPARATOR CORRESPONDING TO CYCLE SLIP

A Programmable Divider with 50% Duty Cycle Unrelated to Dividing Cycle and Its Application to PLL

Design of a threshold automatic compensation circuit for a voltage controlled oscillator using a schmitt-trigger circuit with cmos inverters

共同研究・競争的資金等の研究課題

Study of Digital Locked Loop